GitHub - muhammadaldacher/Layout-Design-of-an-8x8-SRAM-array: The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done
![Single bit‐line 11T SRAM cell for low power and improved stability - Lorenzo - 2020 - IET Computers & Digital Techniques - Wiley Online Library Single bit‐line 11T SRAM cell for low power and improved stability - Lorenzo - 2020 - IET Computers & Digital Techniques - Wiley Online Library](https://ietresearch.onlinelibrary.wiley.com/cms/asset/df2dfe25-ddf2-464d-81b5-ff0da019650d/cdt2bf00275-fig-0004-m.jpg)
Single bit‐line 11T SRAM cell for low power and improved stability - Lorenzo - 2020 - IET Computers & Digital Techniques - Wiley Online Library
![PDF] Design and evaluation of 6T SRAM layout designs at modern nanoscale CMOS processes | Semantic Scholar PDF] Design and evaluation of 6T SRAM layout designs at modern nanoscale CMOS processes | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/6e45b91b92ed01d7f20d40200d282b427a5a7aa3/3-Figure2-1.png)